sprflow

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This document describes the Cadence® synthesis place-and-route (SP&R) flow.

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ch1 Introduction—RTL to GDSII
This document describes the Cadence® synthesis place-and-route (SP&R) flow.

LEF/DEF Language Reference

This manual is a language reference for users of the Cadence® Library Exchange Format
(LEF) and Design Exchange Format (DEF) integrated circuit (IC) description languages.

LEF defines the elements of an IC process technology and associated library of cell models.
DEF defines the elements of an IC design relevant to physical layout, including the netlist and
design constraints. LEF and DEF inputs are in ASCII form.

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About Library Exchange Format Files

A technology LEF file contains all of the LEF technology information for a design, such as
placement and routing design rules, and process information for layers

A cell library LEF file contains the macro and standard cell information for a design.

A technology LEF file contains all of the LEF technology information for a design, such as placement and routing design rules, and process information for layers

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LEF Statement Definitions

Bus Bit Characters
[BUSBITCHARS "delimiterPair" ;]

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Divider Character
[DIVIDERCHAR "character" ;]

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